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te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 1 publication date: sep. 2002 to change products or specifications without notice. revision:0.f sram 128k x 8 high speed cmos static ram features ? fast address access times : 10/12/15ns ? single 3.3v 0.3v power supply ? low power consumption : 110/105/100ma ? ttl i/o compatible ? 2.0v data retention mode ? automatic power-down when deselected ? available packages : 32-pin 300 mil dip/soj & 32-pin sop/tsop-i ? industry standard pin assignment pin configuration tsop-i 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a15 a14 a13 a12 we ce2 a11 vcc nc a10 a9 a8 a7 a6 a5 a4 oe a16 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 vss i/o2 i/o1 i/o0 a0 a1 a2 a3 general description the T14L1024A is a one-megabit density, fast static random access memory organized as 131,072 words by 8 bits. it is designed for use in high performance memory applications such as main memory storage and high speed communication buffers. fabricated using high performance cmos technology, access times down to 10ns are achieved. memory expansion by banking is easily accomplished using the chip enable pins ce1 and ce2. this device is packaged in a standard 32-pin 300 mil dip/soj and 32-pin sop/tsop-i. block diagram pin description symbol description a0 - a16 address inputs i/o0 - i/o7 data inputs/outputs /ce1,ce2 chip select inputs /we write enable /oe output enable vcc power supply vss ground part number examples package speed T14L1024A-10j soj 300mil 10ns T14L1024A-10p tsop-i 8x13.4mm 10ns T14L1024A-10h tsop-i 8x20mm 10ns T14L1024A-10n dip 300mil 10ns T14L1024A-10d sop 10ns a8 a9 a7 a6 a5 a3 a4 a2 a1 a0 i/o0 i/o1 a10 nc 28 27 26 25 23 24 22 21 20 19 18 17 32 29 1 2 3 4 6 5 7 8 9 10 11 12 15 16 vcc a12 a13 a14 a15 a16 i/o7 i/o6 i/o5 a11 ce2 we oe ce1 i/o2 vss 30 31 13 14 i/o4 i/o3 dip / soj / sop decoder a0 a16 ce2 we oe i/o7 vcc data i/o core array vss ce1 i/o0 . . . . . . .
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 2 publication date: sep. 2002 to change products or specifications without notice. revision:0.f dc characteristics absolute maximum ratings parameter sym rating unit power supply voltage vcc -0.5 to 4.6 v input voltage v in -0.5 to vcc+0.5 v output voltage v out -0.5 to vcc+0.5 v operating temperatrue t opr 0 to +70 c storage temperature t stg -55 to +150 c power dissipation p d 1.0 w short circuit output current i out 50 ma truth table ce1 ce2 oe we mode i/o0- i/o7 vcc h x x x not selected high-z i sb, i sb1 x l x x not selected high-z i sb, i sb1 l h h h output disable high-z icc l h l h read data out icc l h x l write data in icc operating characteristics (vcc = 3.3v 0.3v, ta = 0 to 70 c) parameter sym. test conditions min. max. unit power supply voltage vcc 3.0 3.6 v input low voltage v il -0.5 0.8 v input high voltage v ih 2.1 vcc+0.3 v input leakage current i li v in =vss to vcc - 5 ua output leakage current i lo v in =vss to vcc , ce1 = v ih or ce2 = v il or oe = v ih or we = v il - 5 ua output low voltage v ol i ol = 4.0 ma - 0.4 v output high voltage v oh i oh =-2.0 ma 2.4 - v operating power icc ce1 = v il 10ns - 110 ma supply current ce2 = v ih ;f=max 12ns - 105 ma io = 0ma 15ns - 100 ma standby power i sb ce1 = v ih , ce2 = v il , io = 0ma - 25 ma supply current i sb1 vcc = max; ce1 > vcc-0.2v or ce2< vss+0.2v; f=0mhz; io = 0ma - 5 ma note: typical characteristics are at vcc = 3.3v, ta = 25 c
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 3 publication date: sep. 2002 to change products or specifications without notice. revision:0.f recommended operating conditions parameter sym min typ max unit supply voltage vcc typ-0.3 3.3 typ+0.3 v input voltage, low v il -0.3 - 0.8 v input voltage, high v ih 2.1 - vcc+0.3 v ambient temperature t a 0 - 70 c capacitance parameter symbol condition max. unit input capacitance c in v in = 0v 6 pf input/ output capacitance c i/o v out = 0v 8 pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v input rise and fall times 3.0 ns input and output timing reference level 1.5v output load c l =30pf, i oh / i ol = -2ma/4ma ac test loads and waveform rl=50 ohm output zo=50 ohm 30pf r1 319 ohm 3.3v output 5pf including jig and scope r2 353 ohm (for t clz , t olz , t chz , t ohz , t whz , t ow ) vt=1.5v
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 4 publication date: sep. 2002 to change products or specifications without notice. revision:0.f ac characteristics ( v cc =3.3v 0.3v, vss = 0v, ta = 0 to 70 c) (1) read cycle T14L1024A-10 T14L1024A-12 T14L1024A-15 parameter sym. min. max. min. max. min. max. unit read cycle time t rc 10 - 12 - 15 - ns address access time t aa - 10 - 12 - 15 ns chip enable access time t acs - 10 - 12 - 15 ns output enable to output valid t aoe - 6 - 7 - 7 ns chip enable to output in low z t clz* 3 - 3 - 3 - ns output enable to output in low z t olz* 0 - 0 - 0 - ns chip disable to output in high z t chz* - 5 - 6 - 7 ns output disable to output in high z t ohz* - 5 - 6 - 7 ns output hold from address change t oh 3 - 3 - 3 - ns * these parameters are sampled but not 100% tested. (2)write cycle T14L1024A-10 T14L1024A-12 T14L1024A-15 parameter sym. min. max. min. max. min. max. unit write cycle time t wc 10 - 12 - 15 - ns chip enable to end of write t cw 8 - 10 - 11 - ns address valid to end of write t aw 8 - 10 - 11 - ns address setup time t as 0 - 0 - 0 - ns write pulse width t wp 8 - 10 - 11 - ns write recovery time t wr 0 - 0 - 0 - ns data valid to end of write t dw 6 - 8 - 8 - ns data hold from end of write t dh 0 - 0 - 0 - ns write to output in high z t whz* - 5 - 6 - 6 ns output disable to output in high z t ohz* - 5 - 6 - 7 ns output active from end of write t ow 0 - 0 - 0 - ns * these parameters are sampled but not 100% tested.
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 5 publication date: sep. 2002 to change products or specifications without notice. revision:0.f timing waveforms read cycle 1 (address controlled) address d out t oh t aa t rc t oh read cycle 2 (chip enable controlled) ce1 d out ce2 t clz t acs t ohz don't care undefined address t aa t rc t oh oe t chz t aoe t olz
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 6 publication date: sep. 2002 to change products or specifications without notice. revision:0.f write cycle 1 ( oe clock) d out ce1 a ddress ce2 we d in t wc t aw t wr t cw t as t wp t ohz t dh t dw oe write cycle 2 ( oe = v il fixed) d out ce1 a ddress ce2 we d in t wc t aw t wr t cw t as t wp t whz t dh t dw t ow t oh don't care undefined (2 ) (3 ) (1 ,4 )
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 7 publication date: sep. 2002 to change products or specifications without notice. revision:0.f notes: 1. during this period, i/o pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. the data output from d out are the same as the data written to d in during the write cycle. 3. d out provides the read data for the next address. 4. transition is measured 500 mv from steady state with c l = 5pf. this parameter is guaranteed but not 100% tested. 5. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp .
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 8 publication date: sep. 2002 to change products or specifications without notice. revision:0.f package dimensions 32-lead soj (300 mil) symbol dimensions in inches dimensions in mm a 0.140(max) 3.556(max) a1 0.026(min) 0.660(min) a2 0.1000.005 2.5400.127 b 0.018(typ) 0.457(typ) b1 0.028(typ) 0.711(typ) c 0.008(typ) 0.203(typ) d 0.8230.005 20.9040.127 e 0.3350.010 8.5090.254 e1 0.3000.005 7.6200.127 e 0.050(typ) 1.270(typ) l 0.0860.010 2.1840.254 y 0.003(max) 0.076(max)
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 9 publication date: sep. 2002 to change products or specifications without notice. revision:0.f package dimensions 32-lead tsop-i (8x20mm) dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 - 0.006 0.05 - 0.15 a2 0.035 0.040 0.041 0.90 1.00 1.05 b 0.007 0.008 0.011 0.17 0.20 0.27 c 0.004 0.006 0.008 0.10 0.15 0.21 hd 0.787 typ 20.00 typ d 0.724 typ 18.40 typ e 0.315 typ 8.00 typ e 0.020 typ 0.50 typ l 0.020 0.024 0.028 0.50 0.60 0.70 l1 0.032 typ 0.813 typ 0 3 5 0 3 5 hd 1 16 17 32 d "a " c b e a2 a a1 e l l1 d e ta il "a " seating plane seating plane y
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 10 publication date: sep. 2002 to change products or specifications without notice. revision:0.f package dimensions 32-lead tsop-i (8x13.4mm) dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a1 0.002 - 0.006 0.05 - 0.15 a2 0.035 0.040 0.041 0.90 1.00 1.05 b 0.007 0.008 0.011 0.17 0.20 0.27 c 0.004 0.006 0.008 0.10 0.15 0.21 hd 0.528 typ 13.40 typ d 0.465 typ 11.80 typ e 0.315 typ 8.00 typ e 0.020 typ 0.50 typ l 0.020 0.024 0.028 0.50 0.60 0.7 l1 0.032typ 0.813 typ 0 3 5 0 3 5 hd 1 16 17 32 d "a " c b e a2 a a1 e l l1 d e ta il "a " seating plane seating plane y
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 11 publication date: sep. 2002 to change products or specifications without notice. revision:0.f package dimensions 32-lead dip (300 mil) a a1 b b1 b2 b3 c c1 d d1 c2 1 16 17 32 0 b4 dimension in mm dimension in inch symbol min nom max min nom max a - 40.64 41.15 - 1.60 1.62 a1 7.26 7.36 7.46 0.286 0.290 0.294 b - - 5.08 - - 0.200 b1 3.05 3.30 3.56 0.120 0.130 0.140 b2 3.68 3.81 3.94 0.145 0.150 0.155 b3 0.38 - - 0.015 - - b4 - - 1.65 - - 0.065 c 2.29 2.54 2.79 0.090 0.100 0.110 c1 0.41 0.46 0.56 0.016 0.018 0.022 c2 1.47 1.52 1.63 0.58 0.60 0.64 d 7.49 8.00 8.50 0.295 0.315 0.335 d1 10.92 11.43 11.94 0.430 0.450 0.470 0 - 15 0 - 15
te ch tm preliminary T14L1024A tm technology, inc. reserves the right p. 12 publication date: sep. 2002 to change products or specifications without notice. revision:0.f package dimensions 32-lead sop 1 16 17 32 ehe b d s a a2 a1 seating plane e y see detail f le c e1 l e1 detail f dimension in inches dimension in mm symbol min. typ. max min. typ. max. a - - 0.118 - - 3.00 a1 0.004 - - 0.10 - - a2 0.101 0.106 0.111 2.57 2.69 2.82 b 0.014 0.016 0.020 0.36 0.41 0.51 c 0.006 0.008 0.012 0.15 0.20 0.31 d - 0.805 0.817 - 20.45 20.75 e 0.440 0.445 0.450 11.18 11.30 11.43 e 0.044 0.050 0.056 1.12 1.27 1.42 he 0.546 0.556 0.556 13.87 14.12 14.38 l 0.023 0.031 0.039 0.58 0.79 0.99 le 0.047 0.055 0.063 1.19 1.40 1.60 s - - 0.036 - - 0.91 y - - 0.004 - - 0.10 0 - 10 0 - 10 notes : 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension b does not include dambar protrusion / intrusion. 3. dimensions d & e include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec.

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